1. Field of the Invention
The present invention relates to a Digital-to-Analog Converter (DAC) circuit configuration for improving the signal-to-noise ratio when using a DAC in the common bipolar (both positive and negative) mode of operation, thereby improving its absolute accuracy.
2. Description of Related Art
Digital Word Split into Portions
One use of a plurality of DACs in a combined unit is to improve the processing of digital words by breaking up a digital word into higher order and lower order sets of digits and to process each in a separate DAC using voltages divided down by a common ladder of resistors (i.e. a multitap potentiometer.)
For example, U.S. Pat. No. 4,198,622 of Connolly et al for a "Double Digital-to-Analog Converter" shows two digital-to-analog converters coupled in series across a reference potential source with a resistor ladder and a switching tree. A digital word is split into two portions. Each portion operates one switching tree. In FIGS. 4, 4a, and 5 of Connolly et al a circuit is shown which uses a single resistor ladder with two 2-bit DACs having output lines 84 and 91 connected in opposition to a buffer 93 so that the upper two bits have the lower two bits subtracted from them. Since one reference and a common switching tree are used, no noise advantage can be gained. Since Vref and ground are used across the resistor ladder, only a unipolar output is available. To get bipolar operation, an offset reference must be used, increasing the noise. The chief objective of the Connolly et al patent is a parts reduction over the DACS preceding Connolly et al. The subtraction in Connolly et al is actually a partitioning of the ranges between the two DACS. It appears that either addition or subtraction can be used as a matter of architecture in the Connolly et al approach.
Another approach is taught in U.S. Pat. No. 4,494,107 of Kearns et al for "Digital to Analog Converter", which describes a converter which converts two digital words. A ladder network is connected to the plus (+) input of a differential amplifier and another set of digital inputs are connected to the minus (-) input of the same differential amplifier. In the claim of the Kearns patent it is clear that the inputs to the two ladders are a first part of a digital word going to one ladder and a second part of the digital word having its maximum value slightly less than the least change in the first part of the digital word. In summary two DACs and an amplifier are integrated into a single circuit.
An alternative example of a system for using a digital word split into portions is described in U.S. Pat. No. 4,503,421 of Hareyama et al for "Digital to Analog Converter". From one input digital signal that system produces two different digital words. (For example, the most significant bits and one or more subsets of the original digital signal.) These new digital signals are applied to at least two DACs and the DACs' outputs are summed to produce the output of the overall system.
Sub-ranging
Another use of plural DACs is sub-ranging which involves a distinct form of conversion process as described in U.S. Pat. No. 4,430,642 of Weigand et al for "Digital-to-Analog Converter". That patent employs sub-ranging to improve accuracy and offset is used to move and diminish the major transition effects at mid-range of the error arising at the transition between "0" and "1".
Pulse Width Modulation
Elimination of a second harmonic can be achieved by using a plurality of DACs in a different way. U.S. Pat. No. 4,542,371 of Uchikoshi, entitled "Method of Converting a Digital Signal into an Analog Signal and a Converter Therefor" describes pulse width modulation using two DACs to eliminate a second harmonic signal. The two pulse width signal forming circuits combine to operate with a complementing circuit providing complementary digital data preceding the second of the two pulse width signal forming circuits. The complementary outputs are fed to a mixer circuit, to plus (+) and minus (-) inputs thereof respectively, and then the output is filtered to smooth the digital signal into an analog signal. There is only one DAC which comprises the overall circuit just described.
Ping Pong DACs for Digital TV
Rapid changes in DAC outputs can lead to switching transients which can be disruptive to a TV receiver. Another quite different design to solve that problem is found in U.S. Pat. No. 4,591,832 of Fling et al for "Digital-to-Analog Conversion System as for Use in a Digital TV Receiver." The Fling system uses two parallel inputs to DACS which are used on alternate phases to input data to an analog summing circuit very rapidly, faster than one DAC can update the signal. The patent states that the two DACs are operated in ping pong fashion with their outputs linearly summed. The patent states that this design eliminates switch transient contamination and DC offset problems.
A typical DAC contains analog, electrical current outputs weighted in a binary combination of electrical currents. In the bipolar mode, an internal fixed offset current source is used to shift the output from the unipolar mode to the bipolar mode.
The noise of each current source increases with the amplitude of the current from that current source. A DAC operating in a bipolar mode with +/-1 ma. output current is comprised of a set of current sources producing output currents which add to 2 ma., and a fixed offset current source having an output current of -1 ma. Therefore the output of the DAC has the current amplitude equivalent in scale to the scale of the current source of 1 ma., but has a noise amplitude greater than that of a 2 ma. current source. This poor signal-to-noise ratio results in poor accuracy.
Sign Magnitude Method
There is in common use a method of noise reduction while operating in the bipolar mode using DACs such as the ones described below in connection in this invention. With that bipolar method, often called the sign-magnitude method, only one of the two DACs is used in its unipolar mode. Depending on whether a positive or a negative output is desired at any particular time, the DAC output voltage is switched to either an inverting or a non-inverting amplifier. For example, as the DAC is used in the unipolar mode, to obtain the opposite polarity, the DAC output is inverted when the opposite polarity is desired.
The sign magnitude method yields very good noise figures, but it has a serious drawback. When the zero output offset current of the DAC or current-to-voltage converting amplifier drifts away from zero, the final output offset current will change polarity when the output polarity is switched. Consequently, at the transition point from one polarity of output voltage or current) to another, there will be a discontinuity of the final output voltage equal to twice the offset voltage. In other words, the positive offset in the zero value of the DAC will create a positive shift in one polarity, but a negative shift when the output is inverted to the opposite polarity.
As a result using that circuit design, a discontinuity of twice the amplitude of the offset current is experienced when the DAC output current crosses from one polarity to another. The error resulting from this form of discontinuity is generally not correctable, and will cause a serious problem in most applications.
In the conventional use of a current digital-to-analog converter (DAC) in the bipolar mode, the basically unipolar DAC output is offset by connecting a resistor from the DAC output to a reference voltage, producing an offset current equal and opposite to half the full scale current output of the DAC. The output voltage of the operational amplifier is equal and opposite to the product of the combined offset and DAC current and the feedback resistor R1.
DAC Circuit
In reference to FIG. 1, a prior art form of DAC circuit is shown. A data input bus 10 carries data in digital form which passes to digital data buffer 11 from which it is supplied on bus line 12 in parallel to DAC 13. DAC 13 includes a simple digital-to-analog circuit illustrated as a current source CS1 with an output voltage connected between output line 15 and node 9 which is connected to ground. DAC 13 also includes a voltage (reference) source RS providing an offset current (e.g. a Zener diode.) Source RS is connected in series with an offset current resistor ROFF. Source RS and resistor R.sub.OFF are connected in series between output line 14 and through node 9 to ground.
Output line 14 is connected to output line 15 at node 21. Output line 15 is also connected through node 21 to the negative input terminal 20 of an inverting, operational amplifier (op-amp) 17, whose positive input is connected by line 16 through node 9 to ground. The output of op-amp 17 is line 19. Feedback resistor 18 is connected between node 21 and line 19.
In operation, the output line 15 of the DAC 13 is connected to the negative input of op-amp 17 via line 20. The offset current on output line 14 from the DAC 13 is also supplied to node 21 along with the DAC output current on line 15. In this configuration, the offset current from line 14 is always active.
If the total full scale current from the output current from DAC 13 on line 15 is -2 ma, and if the offset current on line 14 is 1 ma, then at - full scale, the DAC current will be turned off, and the total output from the combination would be 1 ma., simply that of the offset current. If the random noise of the offset current is 10 parts per million (ppm), then the output noise is 10 na. If the feedback resistor 18 is 10 kilohms, then the output voltage of the inverting, operational amplifier (op-amp) 17 will be -10 volts, with a noise of 100 nv.
At mid-range, where the desired output is zero, the offset current is 1 ma, the output of DAC 13 on line 15 is -1 ma. Assuming the DAC output on line 15 has 10 ppm of noise, it would have 10 na of output noise; then the total output current of the combination is zero, while the random noise of DAC line 15 and the offset output 14 will be the root sum square of the two noise currents: 14.14 na. Therefore the output, which is zero volts, has a voltage noise of 141.4 nv.
As + full scale of the DAC 13, the DAC current on output line 15 is -2 ma, while the offset current on output line 14 is 1 ma. The net current from the DAC and offset combination is therefore -1 ma. The output voltage is +10 volts on node 19. The noise current of the offset is 10 na as before, while the noise current of the DAC output 15 is 10 ppm, which is na. The total root sum square of the random current noise is 22.36 na, and the output voltage noise is